Abstract
This paper examines self-heating trends in ultra-scaled fully depleted SOI and GOI devices. We introduce a self-consistent model for calculating device temperature, saturation current and intrinsic gate delay. We show that the raised device source/drain can be designed to simultaneously lower device temperature and parasitic capacitance, such that the intrinsic gate delay (CV/I) is optimal. We find that a raised source/drain height approximately 3 times the channel thickness would be desirable both from an electrical and thermal point of view. Optimized GOI devices could provide at least 30 percent performance advantage over similar SOI devices, despite the lower thermal conductivity of the germanium layer.
Original language | English (US) |
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Pages (from-to) | 411-414 |
Number of pages | 4 |
Journal | Technical Digest - International Electron Devices Meeting, IEDM |
State | Published - 2004 |
Externally published | Yes |
Event | IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States Duration: Dec 13 2004 → Dec 15 2004 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry