Electrical modeling and simulation challenges in chip-package codesign

Andreas C. Cangellaris

doi:10.1109/40.710871

Electrical modeling and simulation challenges in chip-package codesign

Andreas C. Cangellaris

Research output: Contribution to journal › Article › peer-review

Abstract

High-performance, multifunctional systems demand novel, often revolutionary, practices in functional-block integration and packaging. Independent chip, package, and board design will have to give way to a holistic approach.

Original language	English (US)
Pages (from-to)	50-59
Number of pages	10
Journal	IEEE Micro
Volume	18
Issue number	4
DOIs	https://doi.org/10.1109/40.710871
State	Published - Jul 1998

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/40.710871

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Electrical modeling and simulation challenges in chip-package codesign

Abstract

ASJC Scopus subject areas

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