Efficient validation input generation in RTL by hybridized source code analysis

Lingyi Liu, Shobha Vasudevan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present HYBRO, an automatic methodology to generate high coverage input vectors for Register Transfer Level (RTL) designs based on branch-coverage directed approach. HYBRO uses dynamic simulation data and static analysis of RTL control flow graphs (CFGs). A concrete simulation is applied over a fixed number of cycles. Instrumented code records the branches covered. The corresponding symbolic trace is extracted from the CFG with an RTL symbolic execution engine. A guard in the symbolic expression is mutated. If the mutated guard has dependent branches that have not already been covered, it is mutated and passed to an SMT solver. A satisfiable assignment generates a valid input vector. We implement the Verilog RTL symbolic execution engine and show that the notion of branch-coverage directed exploration can avoid path explosion caused by previous path-based approach to input vector generation and achieve full branch and more than 90% functional(assertion) coverage quickly on ITC99 benchmark and several Openrisc designs. We also describe two types of optimizations a) dynamic UD chain slicing b)local conflict resolution to speed up HYBRO by 1.6-12 times on different benchmarks.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
Pages1596-1601
Number of pages6
StatePublished - 2011
Event14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 - Grenoble, France
Duration: Mar 14 2011Mar 18 2011

Other

Other14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
CountryFrance
CityGrenoble
Period3/14/113/18/11

Fingerprint

Flow graphs
Guards (shields)
Engines
Computer hardware description languages
Surface mount technology
Level control
Static analysis
Explosions
Concretes
Computer simulation

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Liu, L., & Vasudevan, S. (2011). Efficient validation input generation in RTL by hybridized source code analysis. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 (pp. 1596-1601). [5763253]

Efficient validation input generation in RTL by hybridized source code analysis. / Liu, Lingyi; Vasudevan, Shobha.

Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. 2011. p. 1596-1601 5763253.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, L & Vasudevan, S 2011, Efficient validation input generation in RTL by hybridized source code analysis. in Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011., 5763253, pp. 1596-1601, 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, Grenoble, France, 3/14/11.
Liu L, Vasudevan S. Efficient validation input generation in RTL by hybridized source code analysis. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. 2011. p. 1596-1601. 5763253
Liu, Lingyi ; Vasudevan, Shobha. / Efficient validation input generation in RTL by hybridized source code analysis. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. 2011. pp. 1596-1601
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