Efficient simulation-based optimization of power grid with on-chip voltage regulator

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

IR-drop values of power grid can be reduced through inserting on-chip low-dropout voltage regulators (LDO). In this paper, we explore the optimization of LDOs to meet the IR-drop constraint, where the maximum IR-drop value is less than 10% of power supply. With Cholesky direct solver and SPICE, we propose a method to simulate power grid with LDOs. Based on the simulation method, we develop an efficient flow to optimize the number and locations of the LDOs. Effectiveness of the proposed method is verified by the experimental results. To the best of our knowledge, this is the first work optimizing the number and locations of LDOs to meet the IR-drop constraint.

Original languageEnglish (US)
Title of host publication2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
Pages531-536
Number of pages6
DOIs
StatePublished - Mar 27 2014
Event2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore
Duration: Jan 20 2014Jan 23 2014

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
CountrySingapore
CitySuntec
Period1/20/141/23/14

    Fingerprint

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Yu, T., & Wong, M. D. F. (2014). Efficient simulation-based optimization of power grid with on-chip voltage regulator. In 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings (pp. 531-536). [6742946] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2014.6742946