Abstract
The trend of deep pipelining and multiple instruction issue has made instruction sequencing an extremely critical issue. This paper defines Inline Target Insertion, a specific compiler and pipeline implementation method for Delayed Branches with Squashing. The method is shown to offer two important features not discovered in previous studies. First, branches inserted into branch slots are correctly executed. Second, the execution returns correctly from interrupts or exceptions with only one program counter. These two features make Inline Target Insertion a superior alternative (better performance and less software/hardware complexity) to the conventional delayed branching mechanisms.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1537-1551 |
| Number of pages | 15 |
| Journal | IEEE Transactions on Computers |
| Volume | 41 |
| Issue number | 12 |
| DOIs | |
| State | Published - Dec 1992 |
Keywords
- Branch handling
- code expansion
- deep pipelining
- exception handling
- instruction sequencing
- multiple instruction issue
- profile-based branch prediction
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics
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Cite this
Hwu, W. W., & Chang, P. P. (1992). Efficient Instruction Sequencing with Inline Target Insertion. IEEE Transactions on Computers, 41(12), 1537-1551. https://doi.org/10.1109/12.214662