Efficient HW and SW Interface Design for Convolutional Neural Networks Using High-Level Synthesis and TensorFlow

Mathematics

• Neural Networks 47%
• Hardware Accelerator 34%
• Framework 29%
• Multiprocessing 27%
• Configuration 26%
• Figure of Merit 24%
• Module 22%
• Design 20%
• Multiobjective Optimization Problems 20%
• Parallelism 19%
• Unit 11%
• Model 5%

Engineering & Materials Science

• High level synthesis 64%
• Particle accelerators 51%
• Convolutional neural networks 46%
• Computer hardware 22%
• Convolution 12%
• Clocks 10%