Efficient HW and SW Interface Design for Convolutional Neural Networks Using High-Level Synthesis and TensorFlow

Hardware accelerators have been extensively used for the deployment of convolutional neural networks (CNNs) as they offer speedup by exploiting the parallelism that exists in CNNs. The development of such accelerators spans a large design space and involves a complex execution model that includes software and hardware modules. The figures of merit of an accelerator are its frequency of operation, the number of operations performed per unit time, and various supported configurations and thus designing such accelerators becomes a multi-objective optimization problem. This work presents a systematic approach to developing an efficient framework for CNNs that qualifies such merits and can be scaled to different configurations using Xilinx Vitis-HLS. High-level synthesis (HLS) has proved to be a promising solution to describe large and complex designs in a short time. The presented framework utilizes four copies of a single unified module for executing convolution and pooling in hardware and uses TensorFlow to run certain layers in software using multiprocessing. The framework has been evaluated with Squeezenet 1.0, VGG 16, and Resnet 50 at 250 MHz clock frequency on the Xilinx Alveo U250 board achieving 750 GOPS.