Abstract
We propose a novel buffer insertion algorithm for handling more general networks, whose underlying topology is a directed acyclic graph rather than just a RC tree. The algorithm finds a global buffering which minimizes buffer area while meeting the timing constraints. We use Lagrangian relaxation to translate the timing constraints to a cost in the objective function, and simplify the resulting objective function using the special structure of the problem we are solving. The core of the algorithm is a local refinement procedure, which iteratively computes the optimal buffering for each edge so as to minimize a weighted area and delay objective. The resulting procedure is fast, and takes full advantage of the slack available on noncritical paths.
Original language | English (US) |
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Pages | 210-215 |
Number of pages | 6 |
State | Published - 1999 |
Externally published | Yes |
Event | International Conference on Computer Design (ICCD'99) - Austin, TX, USA Duration: Oct 10 1999 → Oct 13 1999 |
Other
Other | International Conference on Computer Design (ICCD'99) |
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City | Austin, TX, USA |
Period | 10/10/99 → 10/13/99 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering