Effect of on-chip ESD protection on 10 Gb/s receivers

Adam C. Faust, Ankit Srivastava, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Parasitic elements at the input of a high-speed receiver may limit bandwidth. A test chip was designed to quantify the impact of ESD protection on the performance of a 10 Gb/s receiver. Negative capacitance circuits are shown to improve signal integrity and their impact on ESD resiliency is measured.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings - 2011, EOS/ESD 2011
StatePublished - Nov 10 2011
Event2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011 - Anaheim, CA, United States
Duration: Sep 11 2011Sep 16 2011

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Other

Other2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011
CountryUnited States
CityAnaheim, CA
Period9/11/119/16/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Faust, A. C., Srivastava, A., & Rosenbaum, E. (2011). Effect of on-chip ESD protection on 10 Gb/s receivers. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings - 2011, EOS/ESD 2011 [6045578] (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).