Abstract
An efficient technology mapping algorithm that achieves probably optimal delay in the technology mapped circuit using the general delay model is presented. The algorithm is a non-trivial generalization of FlowMap. A key problem in the algorithm is to compute a K-feasible network cut such that the circuit delay on every cut edge is upper-bounded by a specific value. The algorithm is implemented in a lookup-table (LUT) based FPGA technology mapping package called Edge-Map, and Edge-Map is tested on a set of benchmark circuits.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 150-155 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| State | Published - 1994 |
| Externally published | Yes |
| Event | Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA Duration: Nov 6 1994 → Nov 10 1994 |
ASJC Scopus subject areas
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering