@article{70bb897d51e7493292e6a5dff513eac0,
title = "EagerMap: A task mapping algorithm to improve communication and load balancing in clusters of multicore systems",
abstract = "Communication between tasks and load imbalance have been identified as a major challenge for the performance and energy efficiency of parallel applications. A common way to improve communication is to increase its locality, that is, to reduce the distances of data transfers, prioritizing the usage of faster and more efficient local interconnections over remote ones. Regarding load imbalance, cores should execute a similar amount of work. An important problem to be solved in this context is how to determine an optimized mapping of tasks to cluster nodes and cores that increases the overall locality and load balancing. In this article, we propose the EagerMap algorithm to determine task mappings, which is based on a greedy heuristic to match application communication patterns to hardware hierarchies and which can also consider the task load. Compared to previous algorithms, EagerMap is faster, scales better, and supports more types of computer systems, while maintaining the same or better quality of the determined task mapping. EagerMap is therefore an interesting choice for task mapping on a variety of modern parallel architectures.",
keywords = "Clusters, Communication, Locality, Task mapping",
author = "Cruz, {Eduardo H.M.} and Matthias Diener and Pilla, {La{\'e}rcio L.} and Navaux, {Philippe O.A.}",
note = "Funding Information: This research received funding from the EU H2020 Programme and from MCTI/RNP-Brazil under the HPC4E project, grant agreement n.° 689772. It was also supported by Intel. Authors{\textquoteright} addresses: E. H. M. Cruz, Instituto Federal do Paran{\'a} - Campus Paranava{\'i} - Rua Jos{\'e} Felipe Tequinha 1400 - Jardim das Na{\c c}{\~o}es - Cep: 87703-536 - Paranava{\'i} - PR, Brazil; email: eduardo.cruz@ifpr.edu.br; M. Diener, University of Illinois at Urbana-Champaign, 1308 W Main St, Urbana IL, 61801, USA; email: mdiener@illinois.edu; L. L. Pilla, Laboratoire de Recherche en Informatique B{\^a}t 650 Ada Lovelace, Universit{\'e} Paris Sud, 91405 Orsay Cedex France; email: pilla@lri.fr; P. O. A. Navaux, Instituto de Inform{\'a}tica – Universidade Federal do Rio Grande do Sul (UFRGS), Caixa Postal 15.064 – 91.501-970, Porto Alegre – RS, Brazil; email: navaux@inf.ufrgs.br. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. {\textcopyright} 2019 Association for Computing Machinery. 2329-4949/2019/03-ART17 $15.00 https://doi.org/10.1145/3309711 Funding Information: This research received funding from the EU H2020 Programme and from MCTI/RNP-Brazil under the HPC4E project, grant agreement n.° 689772. It was also supported by Intel. Publisher Copyright: {\textcopyright} 2019 Association for Computing Machinery.",
year = "2019",
month = mar,
doi = "10.1145/3309711",
language = "English (US)",
volume = "5",
journal = "ACM Transactions on Parallel Computing",
issn = "2329-4949",
publisher = "Association for Computing Machinery",
number = "4",
}