DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior

Lu Wan, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to the worst-case conditions to guarantee error-free computation but may also lead to very inefficient designs. Recently, there are processor works that over-clock the chip to achieve higher performance to the point where timing errors occur, and then error correction is performed either through circuit-level or microarchitecture-level techniques. This approach in general is referred to as Timing Speculation. In this paper, we propose a new circuit optimization technique "DynaTune" for timing speculation based on the dynamic behavior of a circuit. DynaTune optimizes the most dynamically critical gates of a circuit and improves the circuit's throughput under a fixed power budget. We test this proposed technique with two timing speculation schemes - Telescopic Unit (TU) and Razor Logic (RZ). Experimental results show that applying DynaTune on the Leon3 processor can increase the throughput of critical modules by up to 13% and 20% compared to the timing-speculative and non-timing-speculative results optimized by Synopsys Design Compiler, respectively. For MCNC benchmark circuits, DynaTune combined with TU can provide 9% and 20% throughput gains on average compared to timing-speculative and non-timing-speculative results optimized by Design Compiler. When combined with RZ, DynaTune can achieve 8% and 15% throughput gains on average for above experiments.

Original languageEnglish (US)
Title of host publicationProceedings of the 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, ICCAD 2009
Pages172-179
Number of pages8
StatePublished - Dec 1 2009
Event2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009 - San Jose, CA, United States
Duration: Nov 2 2009Nov 5 2009

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

Other2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009
CountryUnited States
CitySan Jose, CA
Period11/2/0911/5/09

Keywords

  • BDD
  • Dual threshold voltage
  • Logic synthesis
  • Performance
  • Throughput
  • Timing analysis
  • Timing speculation

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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