Dynamic power estimation for deep submicron circuits with process variation

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow glitches consume less power than wide glitches. Glitch width and transition density modeling is further complicated by the effect of process variation. This paper presents a fast and accurate dynamic power estimation method that considers the detailed effect of process variation. First, we extend the probabilistic modeling approach to handle timing variations. Then the power consumption of a logic gate is computed based on the transition waveforms of its inputs. Both mean values and standard deviations of the dynamic power are estimated with high confidence based on accurate device characterization data. Compared with SPICE-based Monte Carlo simulations for small circuits, our power estimator reports power results within 3% error for the mean and 5% error for the standard deviation with six orders of magnitude speedup. For medium and large benchmarks, it is impossible to run Monte Carlo simulations with enough samples due to very long runtime, while our estimator can finish within minutes.

Original languageEnglish (US)
Title of host publication2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages587-592
Number of pages6
DOIs
StatePublished - Apr 28 2010
Event2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China
Duration: Jan 18 2010Jan 21 2010

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
CountryTaiwan, Province of China
CityTaipei
Period1/18/101/21/10

Fingerprint

Networks (circuits)
Electric power utilization
Logic gates
SPICE
Monte Carlo simulation

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Dinh, Q., Chen, D., & Wong, M. D. F. (2010). Dynamic power estimation for deep submicron circuits with process variation. In 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 (pp. 587-592). [5419818] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419818

Dynamic power estimation for deep submicron circuits with process variation. / Dinh, Quang; Chen, Deming; Wong, Martin D F.

2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. 2010. p. 587-592 5419818 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dinh, Q, Chen, D & Wong, MDF 2010, Dynamic power estimation for deep submicron circuits with process variation. in 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010., 5419818, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 587-592, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, Province of China, 1/18/10. https://doi.org/10.1109/ASPDAC.2010.5419818
Dinh Q, Chen D, Wong MDF. Dynamic power estimation for deep submicron circuits with process variation. In 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. 2010. p. 587-592. 5419818. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419818
Dinh, Quang ; Chen, Deming ; Wong, Martin D F. / Dynamic power estimation for deep submicron circuits with process variation. 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. 2010. pp. 587-592 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
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