Dynamic optimization of micro-operations

B. Slechta, D. Crowe, N. Fahs, M. Fertig, G. Muthler, J. Quek, F. Spadini, S. J. Patel, S. S. Lumetta

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Inherent within complex instruction set architectures such as ×86 are inefficiencies that do not exist in a simpler ISA. Modern ×86 implementations decode instructions into one or more micro-operations in order to deal with the complexity of the ISA. Since these micro-operations are not visible to the compiler the stream of micro-operations can contain redundancies even in statically optimized ×86 code. Within a processor implementation, however barriers at the ISA level do not apply, and these redundancies can be removed by optimizing the micro-operation stream. In this paper we explore the opportunities to optimize code at the micro-operation granularity. We execute these micro-operation optimizations using the rePLay Framework as a microarchitectural substrate. Using a simple set of seven optimizations, including two that aggressively and speculatively attempt to remove redundant load instructions, we examine the effects of dynamic optimization of micro-operations using a trace-driven simulation environment. Simulation reveals that across a sampling of SPECint 2000 and real ×86 applications, rePLay is able to reduce micro-operation count by 21% and, in particular load micro-operation count by 22%. These reductions correspond to a boost in observed instruction-level parallelism on an 8-wide optimizing rePLay processor by 17% over a non-optimizing configuration.

Original languageEnglish (US)
Title of host publicationProceedings - 9th International Symposium on High-Performance Computer Architecture, HPCA 2003
PublisherIEEE Computer Society
Number of pages12
ISBN (Electronic)0769518710
StatePublished - 2003
Event9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003 - Anaheim, United States
Duration: Feb 8 2003Feb 12 2003

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897


Other9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003
Country/TerritoryUnited States


  • Application software
  • Computer architecture
  • Decoding
  • Hardware
  • Instruction sets
  • Microarchitecture
  • Parallel processing
  • Performance evaluation
  • Redundancy
  • Registers

ASJC Scopus subject areas

  • Hardware and Architecture


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