TY - GEN
T1 - Dynamic memory disambiguation using the memory conflict buffer
AU - Gallagher, David M.
AU - Chen, William Y.
AU - Mahlke, Scott A.
AU - Gyllenhaal, John C.
AU - Hwu, Wen Mei W.
N1 - Funding Information:
The authors would like to thank Roger Bringmann, Richard Hank, and Grant Haab, along with all members of the IMPACT research group for their comments and suggestions. Special thanks Pohua Chang at Intel Corporation, Tokuzo Kiyohara at Matsushita Electric Industrial Co., Ltd., and to the referees whose comments and suggestions helped to improve the quality of this paper significantly. This research has been supported by the NationaJ Science Foundation (NSF) under grant MIP-9308013, Joint Services Engineering Programs (JSEP) under Contract NOOO14-90-J-1270, Intel Corporation, the AMD 29K Advanced Processor Development Division, Hewlett-Packard, SUN Microsystems, NCR and the National Aeronautics and Space Administration (NASA) under Contract NASA NAG 1-613 in cooperation with the Illinois Computer laboratory for Aerospace Systems and Software (ICLASS). John GyllenhaaJ was also supported by an NSF Graduate Research Fellowship.
PY - 1994/11/1
Y1 - 1994/11/1
N2 - To exploit instruction level parallelism, compilers for VLIW and superscalar processors often employ static code scheduling. However, the available code reordering may be severely restricted due to ambiguous dependence between memory instructions. This paper introduces a simple hardware mechanism, referred to as the memory conj7ict buffer, which facilitates static code scheduling in the presence of memory storelload dependence. Correct program execution is ensured by the memory conflict buffer and repair code provided by the compiler. With this addition, significant speedup over an aggressive code scheduling model can be achieved for both non-numerical and numerical programs.
AB - To exploit instruction level parallelism, compilers for VLIW and superscalar processors often employ static code scheduling. However, the available code reordering may be severely restricted due to ambiguous dependence between memory instructions. This paper introduces a simple hardware mechanism, referred to as the memory conj7ict buffer, which facilitates static code scheduling in the presence of memory storelload dependence. Correct program execution is ensured by the memory conflict buffer and repair code provided by the compiler. With this addition, significant speedup over an aggressive code scheduling model can be achieved for both non-numerical and numerical programs.
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U2 - 10.1145/195473.195534
DO - 10.1145/195473.195534
M3 - Conference contribution
AN - SCOPUS:84988787288
T3 - International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS
SP - 183
EP - 193
BT - Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 1994
PB - Association for Computing Machinery
T2 - 6th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 1994
Y2 - 4 October 1994 through 7 October 1994
ER -