## Abstract

In this paper, dynamic algorithm transformations (DAT's) for designing low-power reconfigurable signal-processing systems are presented. These transformations minimize energy dissipation while maintaining a specified level of mean squared error or signal-to-noise ratio. This is achieved by modeling the nonstationarities in the input as temporal/spatial transitions between states in the input state-space. The reconfigurable hardware fabric is characterized by its configuration state-space. The configurable parameters are taken to be the filter taps, coefficient and data precisions, and supply voltage V _{dd}. An energy-optimal reconfiguration strategy is derived as a mapping from the input to the configuration state-space. In this strategy, taps are powered down starting with the tap with the smallest value of [((w _{k} ^{2}/ε _{m}(w _{k})] (where w _{k} and ε _{m}(w _{k}) are, respectively, the coefficient and energy dissipation of the kth tap). Optimal values for precisions and supply voltage V _{dd} are subsequently computed from the roundoff error and critical path delay requirements, respectively. The DAT-based adaptive filter is employed as a near-end crosstalk (NEXT) canceller in a 155.52-Mb/s asynchronous transfer mode-local area network transceiver over category-3 wiring. Simulation results indicate that the energy savings range from -2% to 87% as the cable length varies from 110 to 40 m, respectively, with an average savings of 69%. An average savings of 62% is achieved for the case where the supply voltage V _{dd} is kept fixed.

Original language | English (US) |
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Pages (from-to) | 463-476 |

Number of pages | 14 |

Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |

Volume | 7 |

Issue number | 4 |

DOIs | |

State | Published - Dec 1999 |

## Keywords

- Algorithm transformations
- Low-power
- Reconfigurable computing
- Signal processing

## ASJC Scopus subject areas

- Software
- Hardware and Architecture
- Electrical and Electronic Engineering