TY - JOUR
T1 - Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance
AU - Zhang, Ming
AU - Shanbhag, Naresh R.
N1 - Funding Information:
Manuscript received November 9, 2005. This work was supported by the Microelectroics Advanced Research Corporation sponsored Gigascale Systems Research Center. This paper was recommended by Associate Editor R. Puri.
PY - 2006/12
Y1 - 2006/12
N2 - Presented is a circuit technique that mitigates the impact of single-event transient (SET) in deep submicrometer circuits with minimal speed, power, and area penalty. The technique combines a novel dual-sampling flip-flop (DSFF) and the skewed CMOS (SCMOS) circuit style. The DSFF and SCMOS are designed to eliminate SETs with the polarity of 1 → 0 and 0 → 1, respectively. We study inverter chain circuits as well as sum-of-products implementation of random logic circuits in a typical 0.18-μm process under the influence of radiation induced soft errors. We quantify the SET tolerance of the proposed technique by using an error map and a recently developed tool soft-error rate analyzer (SERA). The results show that the DSFF incurs no speed penalty, if no SETs have reached the input of DSFF. Otherwise, the DSFF alone eliminates the l→ 0 SETs while incurring a worst case speed and power penalty of 310 ps and 39 μW, respectively. The SCMOS eliminates the 0 → 1 SETs when the skewing factor is greater than four. Thus, the proposed technique potentially eliminates the impact of SETs with both polarities.
AB - Presented is a circuit technique that mitigates the impact of single-event transient (SET) in deep submicrometer circuits with minimal speed, power, and area penalty. The technique combines a novel dual-sampling flip-flop (DSFF) and the skewed CMOS (SCMOS) circuit style. The DSFF and SCMOS are designed to eliminate SETs with the polarity of 1 → 0 and 0 → 1, respectively. We study inverter chain circuits as well as sum-of-products implementation of random logic circuits in a typical 0.18-μm process under the influence of radiation induced soft errors. We quantify the SET tolerance of the proposed technique by using an error map and a recently developed tool soft-error rate analyzer (SERA). The results show that the DSFF incurs no speed penalty, if no SETs have reached the input of DSFF. Otherwise, the DSFF alone eliminates the l→ 0 SETs while incurring a worst case speed and power penalty of 310 ps and 39 μW, respectively. The SCMOS eliminates the 0 → 1 SETs when the skewing factor is greater than four. Thus, the proposed technique potentially eliminates the impact of SETs with both polarities.
KW - Combinational logic circuit
KW - flip-flop
KW - integrated-circuit reliability
KW - latch
KW - single-event transient (SET)
KW - soft-error rate (SER)
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U2 - 10.1109/TCSII.2006.883829
DO - 10.1109/TCSII.2006.883829
M3 - Article
AN - SCOPUS:33947391690
SN - 1549-7747
VL - 53
SP - 1461
EP - 1465
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 12
ER -