Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance

Ming Zhang, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review

Abstract

Presented is a circuit technique that mitigates the impact of single-event transient (SET) in deep submicrometer circuits with minimal speed, power, and area penalty. The technique combines a novel dual-sampling flip-flop (DSFF) and the skewed CMOS (SCMOS) circuit style. The DSFF and SCMOS are designed to eliminate SETs with the polarity of 1 → 0 and 0 → 1, respectively. We study inverter chain circuits as well as sum-of-products implementation of random logic circuits in a typical 0.18-μm process under the influence of radiation induced soft errors. We quantify the SET tolerance of the proposed technique by using an error map and a recently developed tool soft-error rate analyzer (SERA). The results show that the DSFF incurs no speed penalty, if no SETs have reached the input of DSFF. Otherwise, the DSFF alone eliminates the l→ 0 SETs while incurring a worst case speed and power penalty of 310 ps and 39 μW, respectively. The SCMOS eliminates the 0 → 1 SETs when the skewing factor is greater than four. Thus, the proposed technique potentially eliminates the impact of SETs with both polarities.

Original languageEnglish (US)
Pages (from-to)1461-1465
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume53
Issue number12
DOIs
StatePublished - Dec 2006

Keywords

  • Combinational logic circuit
  • flip-flop
  • integrated-circuit reliability
  • latch
  • single-event transient (SET)
  • soft-error rate (SER)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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