DRAMA: An architecture for accelerated processing near memory

Amin Farmahini-Farahani, Jung Ho Ahn, Katherine Morrow, Nam Sung Kim

Research output: Contribution to journalArticlepeer-review


Improving energy efficiency is crucial for both mobile and high-performance computing systems while a large fraction of total energy is consumed to transfer data between storage and processing units. Thus, reducing data transfers across the memory hierarchy of a processor (i.e., off-chip memory, on-chip caches, and register file) can greatly improve the energy efficiency. To this end, we propose an architecture, DRAMA, that 3D-stacks coarse-grain reconfigurable accelerators (CGRAs) atop off-chip DRAM devices. DRAMA does not require changes to the DRAM device architecture, apart from through-silicon vias (TSVs) that connect the DRAM device's internal I/O bus to the CGRA layer. We demonstrate that DRAMA can reduce the energy consumption to transfer data across the memory hierarchy by 66-95 percent while achieving speedups of up to 18× over a commodity processor.

Original languageEnglish (US)
Article number6846276
Pages (from-to)26-29
Number of pages4
JournalIEEE Computer Architecture Letters
Issue number1
StatePublished - Jan 1 2015
Externally publishedYes


  • 3D-stacking
  • DRAM
  • Near memory processing
  • accelerator
  • energy-efficient computing

ASJC Scopus subject areas

  • Hardware and Architecture

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