DML: Dynamic Partial Reconfiguration with Scalable Task Scheduling for Multi-Applications on FPGAs

With the increasing complexity of applications and the adoption of FPGAs in the cloud, there is a need to efficiently utilize the FPGA resources and share a single FPGA across multiple applications. Thus, there is a renewed interest to deploy dynamic partial reconfiguration (DPR) for FPGA-based hardware. In this work, we present Doing More with Less (DML) - a methodology for scheduling heterogeneous tasks across an FPGA in a resource efficient manner while effectively hiding the latency of DPR. With the help of an integer linear programming (ILP) based scheduler, we demonstrate the mapping of diverse workloads in both cloud and edge-like scenarios. Our novel contributions include enabling IP-level pipelining and parallelization in our scheduler to exploit parallelism available within batches of work, and strategies to map multiple applications simultaneously. We consider the application of DML on real-world benchmarks on both small (a Zedboard) and large (a ZCU106) FPGAs, across different workload batching and multiple-application scenarios, and demonstrate an average speedup of 5X and up to 7.65X on a ZCU106 via our scheduling strategies. We also demonstrate the scalability of DML by simultaneously mapping multiple applications to an FPGA and explore different approaches to sharing resources between applications.