Strain in electronic devices is receiving renewed interest due to the advantageous effects of strain on carrier mobility, and therefore drive current. However, the physics of strain incorporation, by definition, introduces the physics of strain relief. At typical CMOS process temperatures, semiconductors become ductile, and therefore dislocation nucleation and glide are the most common means of plastic relaxation. To obtain the highest levels of strain, dislocation nucleation and propagation must be avoided. It can be advantageous to create alternative lattice constants for creating strain in other regions, in which case plastic deformation is purposely created in the structure and dislocation sites must be managed. If the goal for the particular device is to create completely relaxed lattice constants, we show global and local methods to control threading dislocation densities. We also show methods to achieve the opposite, i.e. larger values of strain, higher than the level expected in equilibrium. By understanding the nature of dislocation nucleation and propagation, we can overcome future dislocation engineering challenges for new materials systems such as III-V MISFIT heterostructures.