Direct transistor-level layout for digital blocks

Prakash Gopalakrishnan, Robin A Rutenbar

Research output: Book/ReportBook

Abstract

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

Original languageEnglish (US)
PublisherSpringer US
Number of pages125
ISBN (Print)9781402076657
DOIs
StatePublished - Dec 1 2005

Fingerprint

Transistors
MOS devices
Digital circuits
Computer aided design
Defects
Networks (circuits)

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Gopalakrishnan, P., & Rutenbar, R. A. (2005). Direct transistor-level layout for digital blocks. Springer US. https://doi.org/10.1007/b117054

Direct transistor-level layout for digital blocks. / Gopalakrishnan, Prakash; Rutenbar, Robin A.

Springer US, 2005. 125 p.

Research output: Book/ReportBook

Gopalakrishnan, P & Rutenbar, RA 2005, Direct transistor-level layout for digital blocks. Springer US. https://doi.org/10.1007/b117054
Gopalakrishnan P, Rutenbar RA. Direct transistor-level layout for digital blocks. Springer US, 2005. 125 p. https://doi.org/10.1007/b117054
Gopalakrishnan, Prakash ; Rutenbar, Robin A. / Direct transistor-level layout for digital blocks. Springer US, 2005. 125 p.
@book{adc5ebf064754bd186c54d3bc66d22db,
title = "Direct transistor-level layout for digital blocks",
abstract = "Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.",
author = "Prakash Gopalakrishnan and Rutenbar, {Robin A}",
year = "2005",
month = "12",
day = "1",
doi = "10.1007/b117054",
language = "English (US)",
isbn = "9781402076657",
publisher = "Springer US",

}

TY - BOOK

T1 - Direct transistor-level layout for digital blocks

AU - Gopalakrishnan, Prakash

AU - Rutenbar, Robin A

PY - 2005/12/1

Y1 - 2005/12/1

N2 - Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

AB - Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

UR - http://www.scopus.com/inward/record.url?scp=84891436525&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84891436525&partnerID=8YFLogxK

U2 - 10.1007/b117054

DO - 10.1007/b117054

M3 - Book

AN - SCOPUS:84891436525

SN - 9781402076657

BT - Direct transistor-level layout for digital blocks

PB - Springer US

ER -