TY - JOUR
T1 - Digital's DECchip 21066
T2 - The first cost-focused Alpha AXP chip
AU - McKinney, Dina L.
AU - Bhaiwala, Masooma
AU - Chui, Kwong Tak A.
AU - Houghton, Christopher L.
AU - Mullens, James R.
AU - Leibholz, Daniel L.
AU - Patel, Sanjay J.
AU - Ramey, Delvan A.
AU - Rosenbluth, Mark B.
PY - 1994/12
Y1 - 1994/12
N2 - The DECchip 21066 microprocessor is the first Alpha AXP microprocessor to target cost-focused system applications and the second in a family of chips to implement the Alpha AXP architecture. The chip is a 0.675-micrometer (μm), CMOS-based, superscalar, superpipelined processor that uses dual instruction issue. It incorporates a high level of system integration to provide best-in-class system performance for low-cost system applications. The DECchip 21066 microprocessor integrates on-chip, fully pipelined, integer and floating-point processors, a high-bandwidth memory controller, an industry-standard PCI I/O controller, graphics-assisting hardware, internal instruction and data caches, and an external cache controller. Cost-saving packaging techniques and an on-chip, analog phase-locked loop enable the chip to meet the cost demands of personal computers and desktop systems. This paper discusses the trade-offs and results of the design, verification, and implementation of the DECchip 21066 microprocessor.
AB - The DECchip 21066 microprocessor is the first Alpha AXP microprocessor to target cost-focused system applications and the second in a family of chips to implement the Alpha AXP architecture. The chip is a 0.675-micrometer (μm), CMOS-based, superscalar, superpipelined processor that uses dual instruction issue. It incorporates a high level of system integration to provide best-in-class system performance for low-cost system applications. The DECchip 21066 microprocessor integrates on-chip, fully pipelined, integer and floating-point processors, a high-bandwidth memory controller, an industry-standard PCI I/O controller, graphics-assisting hardware, internal instruction and data caches, and an external cache controller. Cost-saving packaging techniques and an on-chip, analog phase-locked loop enable the chip to meet the cost demands of personal computers and desktop systems. This paper discusses the trade-offs and results of the design, verification, and implementation of the DECchip 21066 microprocessor.
UR - http://www.scopus.com/inward/record.url?scp=0028676269&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0028676269&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0028676269
SN - 0898-901X
VL - 6
SP - 66
EP - 77
JO - Digital Technical Journal
JF - Digital Technical Journal
IS - 1
ER -