Digitally-enhanced phase-locking circuits

Pavan Kumar Hanumolu; Gu Yeon Wei; Un Ku Moon; Kartikeya Mayaram

doi:10.1109/CICC.2007.4405753

Digitally-enhanced phase-locking circuits

Pavan Kumar Hanumolu, Gu Yeon Wei, Un Ku Moon, Kartikeya Mayaram

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) Implemented In deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed In detail. The Implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs In digital systems requiring high-performance PLLs.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	361-368
Number of pages	8
ISBN (Print)	1424407869, 9781424407866
DOIs	https://doi.org/10.1109/CICC.2007.4405753
State	Published - 2007
Externally published	Yes
Event	2007 IEEE Custom Integrated Circuits Conference, CICC - San Jose, CA, United States Duration: Sep 16 2007 → Sep 19 2007

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	2007 IEEE Custom Integrated Circuits Conference, CICC
Country/Territory	United States
City	San Jose, CA
Period	9/16/07 → 9/19/07

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/CICC.2007.4405753

Library availability

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Hanumolu, P. K., Wei, G. Y., Moon, U. K., & Mayaram, K. (2007). Digitally-enhanced phase-locking circuits. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC (pp. 361-368). Article 4405753 (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405753

Digitally-enhanced phase-locking circuits. / Hanumolu, Pavan Kumar; Wei, Gu Yeon; Moon, Un Ku et al.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC. Institute of Electrical and Electronics Engineers Inc., 2007. p. 361-368 4405753 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hanumolu, PK, Wei, GY, Moon, UK & Mayaram, K 2007, Digitally-enhanced phase-locking circuits. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC., 4405753, Proceedings of the Custom Integrated Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 361-368, 2007 IEEE Custom Integrated Circuits Conference, CICC, San Jose, CA, United States, 9/16/07. https://doi.org/10.1109/CICC.2007.4405753

@inproceedings{a98761d7a4b547b4bc0a3a9c1deef29e,

title = "Digitally-enhanced phase-locking circuits",

abstract = "In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) Implemented In deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed In detail. The Implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs In digital systems requiring high-performance PLLs.",

author = "Hanumolu, {Pavan Kumar} and Wei, {Gu Yeon} and Moon, {Un Ku} and Kartikeya Mayaram",

note = "Publisher Copyright: {\textcopyright} 2007 IEEE.; 2007 IEEE Custom Integrated Circuits Conference, CICC ; Conference date: 16-09-2007 Through 19-09-2007",

year = "2007",

doi = "10.1109/CICC.2007.4405753",

language = "English (US)",

isbn = "1424407869",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "361--368",

booktitle = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC",

address = "United States",

}

TY - GEN

T1 - Digitally-enhanced phase-locking circuits

AU - Hanumolu, Pavan Kumar

AU - Wei, Gu Yeon

AU - Moon, Un Ku

AU - Mayaram, Kartikeya

PY - 2007

Y1 - 2007

N2 - In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) Implemented In deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed In detail. The Implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs In digital systems requiring high-performance PLLs.

AB - In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) Implemented In deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed In detail. The Implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs In digital systems requiring high-performance PLLs.

UR - http://www.scopus.com/inward/record.url?scp=39549094525&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=39549094525&partnerID=8YFLogxK

U2 - 10.1109/CICC.2007.4405753

DO - 10.1109/CICC.2007.4405753

M3 - Conference contribution

AN - SCOPUS:39549094525

SN - 1424407869

SN - 9781424407866

T3 - Proceedings of the Custom Integrated Circuits Conference

SP - 361

EP - 368

BT - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2007 IEEE Custom Integrated Circuits Conference, CICC

Y2 - 16 September 2007 through 19 September 2007

ER -

Digitally-enhanced phase-locking circuits

Abstract

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