Digitally-enhanced phase-locking circuits

Pavan Kumar Hanumolu, Gu Yeon Wei, Un Ku Moon, Kartikeya Mayaram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) Implemented In deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed In detail. The Implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs In digital systems requiring high-performance PLLs.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages361-368
Number of pages8
ISBN (Print)1424407869, 9781424407866
DOIs
StatePublished - 2007
Externally publishedYes
Event2007 IEEE Custom Integrated Circuits Conference, CICC - San Jose, CA, United States
Duration: Sep 16 2007Sep 19 2007

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

Conference2007 IEEE Custom Integrated Circuits Conference, CICC
Country/TerritoryUnited States
CitySan Jose, CA
Period9/16/079/19/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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