Digital Clock and Data Recovery Circuits for Optical Links

Guanghua Shu, Woo Seok Choi, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Clock and Data Recovery (CDR) circuits perform the function of recovering clock and re-timing received data in optical links. These CDRs must be capable of tolerating large input jitter (high JTOL), filter input jitter (low JTRAN with no jitter peaking) and in burst-mode applications be capable of phase locking in a very short time. In this paper, we elucidate these design tradeoffs and present various CDR architectures that can overcome them. Specifically, D/PLL CDR architecture that achieves high JTOL, low JTRAN, and no jitter peaking is described. A new burst-mode CDR that can lock instantaneously while filtering input jitter is also discussed.

Original languageEnglish (US)
Title of host publication2016 IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2016 - Technical Digest
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509016082
DOIs
StatePublished - Nov 21 2016
Event2016 IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2016 - Austin, United States
Duration: Oct 23 2016Oct 26 2016

Publication series

NameTechnical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
Volume2016-November
ISSN (Print)1550-8781

Other

Other2016 IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2016
CountryUnited States
CityAustin
Period10/23/1610/26/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Shu, G., Choi, W. S., & Hanumolu, P. K. (2016). Digital Clock and Data Recovery Circuits for Optical Links. In 2016 IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2016 - Technical Digest [7751036] (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC; Vol. 2016-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSICS.2016.7751036