Digital clock and data recovery circuits

Saurabh Saxena, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingChapter


In this chapter, we mostly discussed 2X oversampling digital CDRs, which required multiple high-frequency clock phases for data and edge sampling. In contrast, baud-rate CDRs employ a single clock phase for data and clock recovery, thereby reducing the power consumed in multiphase clock generation and distribution circuits. Interested readers can read more about baud-rate CDRs, their benefits and drawbacks.

Original languageEnglish (US)
Title of host publicationPhase-Locked Frequency Generation and Clocking
PublisherInstitution of Engineering and Technology
Number of pages30
ISBN (Electronic)9781785618857
StatePublished - Jan 1 2020


  • Clock and data recovery circuits
  • Clocks
  • Digital circuits

ASJC Scopus subject areas

  • General Engineering


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