Abstract

This paper examines the accuracy of a discrete logic-level fault model often assumed in gate-level or discrete timing simulation. The analysis is done by comparing the faulty behavior predicted by the discrete model to that predicted by a circuit-level SPICE model whose accuracy is generally accepted. The comparison is made at both the subcircuit level, by measuring latch errors, and the system level, by measuring pin errors and data register errors, using the Motorola MC68000 as the target system. The results of the analysis show that the behavior predicted by the discrete model varies significantly from that of the circuit-level model when the injection site has multiple propagation paths to the circuit outputs (or latches) or is an internal node of one of the logic gates, even if the pulse width of the discrete transient is carefully chosen. However, the two models can be made to match for injection sites that are gate inputs or outputs and have only a single propagation path to circuit outputs. The differences in the latch errors predicted by the two models at the subcircuit level lead to over a 40% difference in the number of predicted pin errors and a 50% difference in the number of data errors predicted at the system level.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Symposium on Fault-Tolerant Computing
PublisherPubl by IEEE
Pages86-94
Number of pages9
ISBN (Print)0818655224
StatePublished - Jan 1 1994
EventProceedings of the 24th International Symposium on Fault-Tolerant Computing - Austin, TX, USA
Duration: Jun 15 1994Jun 17 1994

Publication series

NameDigest of Papers - International Symposium on Fault-Tolerant Computing
ISSN (Print)0731-3071

Other

OtherProceedings of the 24th International Symposium on Fault-Tolerant Computing
CityAustin, TX, USA
Period6/15/946/17/94

ASJC Scopus subject areas

  • Hardware and Architecture
  • Engineering(all)

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  • Cite this

    Ries, G. L., Choi, G. S., & Iyer, R. K. (1994). Device-level transient fault modeling. In Digest of Papers - International Symposium on Fault-Tolerant Computing (pp. 86-94). (Digest of Papers - International Symposium on Fault-Tolerant Computing). Publ by IEEE.