TY - GEN

T1 - Device-level transient fault modeling

AU - Ries, Gregory L.

AU - Choi, Gwan S.

AU - Iyer, Ravishankar K.

PY - 1994/1/1

Y1 - 1994/1/1

N2 - This paper examines the accuracy of a discrete logic-level fault model often assumed in gate-level or discrete timing simulation. The analysis is done by comparing the faulty behavior predicted by the discrete model to that predicted by a circuit-level SPICE model whose accuracy is generally accepted. The comparison is made at both the subcircuit level, by measuring latch errors, and the system level, by measuring pin errors and data register errors, using the Motorola MC68000 as the target system. The results of the analysis show that the behavior predicted by the discrete model varies significantly from that of the circuit-level model when the injection site has multiple propagation paths to the circuit outputs (or latches) or is an internal node of one of the logic gates, even if the pulse width of the discrete transient is carefully chosen. However, the two models can be made to match for injection sites that are gate inputs or outputs and have only a single propagation path to circuit outputs. The differences in the latch errors predicted by the two models at the subcircuit level lead to over a 40% difference in the number of predicted pin errors and a 50% difference in the number of data errors predicted at the system level.

AB - This paper examines the accuracy of a discrete logic-level fault model often assumed in gate-level or discrete timing simulation. The analysis is done by comparing the faulty behavior predicted by the discrete model to that predicted by a circuit-level SPICE model whose accuracy is generally accepted. The comparison is made at both the subcircuit level, by measuring latch errors, and the system level, by measuring pin errors and data register errors, using the Motorola MC68000 as the target system. The results of the analysis show that the behavior predicted by the discrete model varies significantly from that of the circuit-level model when the injection site has multiple propagation paths to the circuit outputs (or latches) or is an internal node of one of the logic gates, even if the pulse width of the discrete transient is carefully chosen. However, the two models can be made to match for injection sites that are gate inputs or outputs and have only a single propagation path to circuit outputs. The differences in the latch errors predicted by the two models at the subcircuit level lead to over a 40% difference in the number of predicted pin errors and a 50% difference in the number of data errors predicted at the system level.

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M3 - Conference contribution

AN - SCOPUS:0027929899

SN - 0818655224

T3 - Digest of Papers - International Symposium on Fault-Tolerant Computing

SP - 86

EP - 94

BT - Digest of Papers - International Symposium on Fault-Tolerant Computing

PB - Publ by IEEE

T2 - Proceedings of the 24th International Symposium on Fault-Tolerant Computing

Y2 - 15 June 1994 through 17 June 1994

ER -