Device-level early floorplanning algorithms for RF circuits

Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley

Research output: Contribution to conferencePaperpeer-review

Abstract

High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performance requires careful control of the lowest-level geometric features - wire bends, precise length, proximity, planarity, etc. - we suggest a new layout strategy for these circuits: early floorplanning at the device level. This paper develops a floorplanner for RF circuits based on a genetic algorithm (GA) that supports fully simultaneous placement and routing. The GA evolves slicing-style floorplans comprising devices and planned areas for wire meanders. Each floorplan candidate is fully routed with a gridless, detailed maze-router which can dynamically resize the floorplan as necessary. Experimental results demonstrate the ability of this approach to successfully optimize for wire planarity, realize multiple constraints on net lengths or phases, and achieve reasonable area in modest CPU times.

Original languageEnglish (US)
Pages57-64
Number of pages8
DOIs
StatePublished - 1998
EventProceedings of the 1998 International Symposium on Physical Design, ISPD-98 - Monterey, CA, USA
Duration: Apr 6 1998Apr 8 1998

Other

OtherProceedings of the 1998 International Symposium on Physical Design, ISPD-98
CityMonterey, CA, USA
Period4/6/984/8/98

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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