Device-level early floorplanning algorithms for rf circuits

Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley

Research output: Contribution to journalConference articlepeer-review


High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performance requires careful control of the lowest-level geometric featureswire bends, precise length, planarity, etc., we suggest a new layout strategy for these circuits: early floorplanning at the device level. This paper develops a floorplanner for radio-frequency circuits based on a genetic algorithm (GA) that supports fully simultaneous placement and routing. The GA evolves slicingstyle floor plans comprising devices and planned areas for wire meanders. Each floorplan candidate is fully routed with a gridless, detailed maze-router which can dynamically resize the floorplan as necessary. Experimental results demonstrate the ability of this approach to successfully optimize for wire planarity, realize multiple constraints on net lengths or phases, and achieve reasonable area in modest CPU times.

Original languageEnglish (US)
Pages (from-to)375-388
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number4
StatePublished - 1999
Externally publishedYes
EventProceedings of the 1998 International Symposium on Physical Design, ISPD-98 - Monterey, CA, United States
Duration: Apr 6 1998Apr 8 1998


  • Algorithms
  • Integrated circuit layout
  • Routing

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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