Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis

Zelei Sun, Keith Campbell, Wei Zuo, Kyle Rupnow, Swathi Gurumani, Frederic Doucet, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

High-level synthesis (HLS) promises high-quality hardware with minimal development effort. In this paper, we evaluate the current state-of-the-art in HLS and design techniques based on software references and architecture references. We present a software reference study developing a JPEG encoder from pre-existing software, and an architecture reference study developing an AES block encryption module from scratch in SystemC and SystemVerilog based on a desired architecture. Additionally, we develop micro-benchmarks to demonstrate best-practices in C coding styles that produce high-quality hardware with minimal development effort. Finally, we suggest language, tool, and methodology improvements to improve upon the current state-of-the-art in HLS.

Original languageEnglish (US)
Title of host publication2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages218-225
Number of pages8
ISBN (Electronic)9781467395694
DOIs
StatePublished - Mar 7 2016
Event21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao
Duration: Jan 25 2016Jan 28 2016

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume25-28-January-2016

Other

Other21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
CountryMacao
CityMacao
Period1/25/161/28/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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  • Cite this

    Sun, Z., Campbell, K., Zuo, W., Rupnow, K., Gurumani, S., Doucet, F., & Chen, D. (2016). Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 (pp. 218-225). [7428014] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2016.7428014