Designing a 2048-Chiplet, 14336-Core Waferscale Processor

Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, Puneet Gupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today's highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant performance and cost benefits. However, designing such a system has several challenges such as power delivery, clock distribution, waferscale-network design, design for testability and fault-tolerance. In this work, we discuss these challenges and the solutions we employed to design a 2048-chiplet, 14,336-core waferscale processor system.

Original languageEnglish (US)
Title of host publication2021 58th ACM/IEEE Design Automation Conference, DAC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)9781665432740
StatePublished - Dec 5 2021
Externally publishedYes
Event58th ACM/IEEE Design Automation Conference, DAC 2021 - San Francisco, United States
Duration: Dec 5 2021Dec 9 2021

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Conference58th ACM/IEEE Design Automation Conference, DAC 2021
Country/TerritoryUnited States
CitySan Francisco


  • Chiplet Assembly
  • Silicon Interconnect Fabric
  • Waferscale Processors

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation


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