Design Space Exploration for Chiplet-Assembly-Based Processors

Saptadeep Pal, Daniel Petrisko, Rakesh Kumar, Puneet Gupta

Research output: Contribution to journalArticle

Abstract

Recent advancements in 2.5-D integration technologies have made chiplet assembly a viable system design approach. Chiplet assembly is emerging as a new paradigm for heterogeneous design at lower cost, design effort, and turnaround time and enables low-cost customization of hardware. However, the success of this approach depends on identifying a minimum chiplet set which delivers these benefits. We develop the first microarchitectural design space exploration framework for chiplet assembly-based processors which enables us to identify the minimum set of chiplets to design and manufacture. Since chiplet assembly makes heterogeneous technology and cost-effective application-dependent customization possible, we show the benefits of using multiple systems built from multiple chiplets to service diverse workloads (up to 35% improvement in energy-delay product over a single best system) and advantages of chiplet assembly approaches over system-on-chip (SoC) methodology in terms of total cost (up to 72% improvement in cost) while satisfying the energy and performance constraints of individual applications.

Original languageEnglish (US)
Article number8998304
Pages (from-to)1062-1073
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume28
Issue number4
DOIs
StatePublished - Apr 2020
Externally publishedYes

Keywords

  • 2.5-D integration
  • chiplet assembly
  • micro-architectural design space exploration (DSE)
  • multichiplet optimization

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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