Design of the processing node of the PTAH 64 parallel computer

F. Cappello, J. L. Bechennec, J. L. Glavitto

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents the design of the Processing Node (PN) for an implementation of the PTAH architectural model with 64 PNs. The PTAH architecture is presented. The requirements of a 64 PNs implementation are derived. The design tradeoff for the global Processing Node architecture, the control system, the Floating Point and Integer Unit and the data memory is discussed. Finaly the instruction formats are presented.

Original languageEnglish (US)
Pages (from-to)105-111
Number of pages7
JournalMicroprocessing and Microprogramming
Volume35
Issue number1-5
DOIs
StatePublished - Sep 1992
Externally publishedYes

Keywords

  • Distributed and shared memory parallel computer
  • Memory interleaving
  • Superpipeline processor
  • Zero delay branching

ASJC Scopus subject areas

  • Engineering(all)

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