Design of the processing node of the PTAH 64 parallel computer

F. Cappello; J. L. Bechennec; J. L. Glavitto

doi:10.1016/0165-6074(92)90301-M

Design of the processing node of the PTAH 64 parallel computer

F. Cappello, J. L. Bechennec, J. L. Glavitto

Research output: Contribution to journal › Article › peer-review

Abstract

This paper presents the design of the Processing Node (PN) for an implementation of the PTAH architectural model with 64 PNs. The PTAH architecture is presented. The requirements of a 64 PNs implementation are derived. The design tradeoff for the global Processing Node architecture, the control system, the Floating Point and Integer Unit and the data memory is discussed. Finaly the instruction formats are presented.

Original language	English (US)
Pages (from-to)	105-111
Number of pages	7
Journal	Microprocessing and Microprogramming
Volume	35
Issue number	1-5
DOIs	https://doi.org/10.1016/0165-6074(92)90301-M
State	Published - Sep 1992
Externally published	Yes

Keywords

Distributed and shared memory parallel computer
Memory interleaving
Superpipeline processor
Zero delay branching

ASJC Scopus subject areas

General Engineering

Online availability

10.1016/0165-6074(92)90301-M

Library availability

Discover UIUC Full Text

Cite this

@article{3fd335d518f843dd9e4d783fd976718c,

title = "Design of the processing node of the PTAH 64 parallel computer",

abstract = "This paper presents the design of the Processing Node (PN) for an implementation of the PTAH architectural model with 64 PNs. The PTAH architecture is presented. The requirements of a 64 PNs implementation are derived. The design tradeoff for the global Processing Node architecture, the control system, the Floating Point and Integer Unit and the data memory is discussed. Finaly the instruction formats are presented.",

keywords = "Distributed and shared memory parallel computer, Memory interleaving, Superpipeline processor, Zero delay branching",

author = "F. Cappello and Bechennec, {J. L.} and Glavitto, {J. L.}",

year = "1992",

month = sep,

doi = "10.1016/0165-6074(92)90301-M",

language = "English (US)",

volume = "35",

pages = "105--111",

journal = "Microprocessing and Microprogramming",

issn = "0165-6074",

publisher = "Elsevier B.V.",

number = "1-5",

}

TY - JOUR

T1 - Design of the processing node of the PTAH 64 parallel computer

AU - Cappello, F.

AU - Bechennec, J. L.

AU - Glavitto, J. L.

PY - 1992/9

Y1 - 1992/9

N2 - This paper presents the design of the Processing Node (PN) for an implementation of the PTAH architectural model with 64 PNs. The PTAH architecture is presented. The requirements of a 64 PNs implementation are derived. The design tradeoff for the global Processing Node architecture, the control system, the Floating Point and Integer Unit and the data memory is discussed. Finaly the instruction formats are presented.

AB - This paper presents the design of the Processing Node (PN) for an implementation of the PTAH architectural model with 64 PNs. The PTAH architecture is presented. The requirements of a 64 PNs implementation are derived. The design tradeoff for the global Processing Node architecture, the control system, the Floating Point and Integer Unit and the data memory is discussed. Finaly the instruction formats are presented.

KW - Distributed and shared memory parallel computer

KW - Memory interleaving

KW - Superpipeline processor

KW - Zero delay branching

UR - http://www.scopus.com/inward/record.url?scp=0026915138&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026915138&partnerID=8YFLogxK

U2 - 10.1016/0165-6074(92)90301-M

DO - 10.1016/0165-6074(92)90301-M

M3 - Article

AN - SCOPUS:0026915138

SN - 0165-6074

VL - 35

SP - 105

EP - 111

JO - Microprocessing and Microprogramming

JF - Microprocessing and Microprogramming

IS - 1-5

ER -

Design of the processing node of the PTAH 64 parallel computer

Abstract

Keywords

ASJC Scopus subject areas

Online availability

Library availability

Related links

Fingerprint

Cite this