Design of selective-area growth compatible fully-vertical GaN p-i-n diodes with dielectric vertical sidewall appended edge termination schemes

While a slew of edge termination schemes for gallium nitride (GaN) power devices have been proposed and experimentally demonstrated to date, all of them suffer from the inability to achieve breakdown voltage close to ideal parallel-plane breakdown voltage. Further, they are exclusively processed using implantation or dry etching based methods, both of which are known to introduce additional defects and lattice damage leading to large leakage components. In this work, we develop and design novel dielectric vertical sidewall appended edge termination (DiVSET) schemes that are surface-charge resilient and capable of achieving ideal parallel-plane breakdown voltage. These edge termination schemes are compatible with plasma-assisted molecular-beam epitaxy facilitated silicon nitride shadowed selective-area growth (SNS-SAG) processing protocol, recently developed by us. The SNS-SAG protocol is uniquely capable of processing smooth, lattice damage-free GaN interfaces and vertical sidewalls that can reduce the leakage current by several orders of magnitude compared to conventional implant and dry etching based GaN processing. Together with the SNS-SAG processing, the DiVSET schemes offer an enabling technology for high-performance ultra-low leakage GaN power devices.