Design of energy-efficient high-speed links via forward error correction

Rajan Narasimha, Naresh Shanbhag

Research output: Contribution to journalArticle

Abstract

In this brief, we show that forward error correction (FEC) can reduce power in high-speed serial links. This is achieved by trading off the FEC coding gain with specifications on transmit swing, analog-to-digital converter (ADC) precision, jitter tolerance, receive amplification, and by enabling higher signal constellations. For a 20-in FR4 link carrying 10-Gb/s data, we demonstrate: 1) an 18-mW/Gb/s savings in the ADC; 2) a 1-mW/Gb/s reduction in transmit driver power; 3) up to 6× improvement in transmit jitter tolerance; and 4) a 25- to 40-mV improvement in comparator offset tolerance with 3 × smaller swing.

Original languageEnglish (US)
Article number5464335
Pages (from-to)359-363
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume57
Issue number5
DOIs
StatePublished - May 1 2010

Keywords

  • Analog-to-digital converter
  • Backplane transceivers
  • Clock jitter
  • Comparative offset
  • Energy-efficiency
  • Forward error correction
  • High-speed links
  • Transmit driver

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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