Abstract
In this brief, we show that forward error correction (FEC) can reduce power in high-speed serial links. This is achieved by trading off the FEC coding gain with specifications on transmit swing, analog-to-digital converter (ADC) precision, jitter tolerance, receive amplification, and by enabling higher signal constellations. For a 20-in FR4 link carrying 10-Gb/s data, we demonstrate: 1) an 18-mW/Gb/s savings in the ADC; 2) a 1-mW/Gb/s reduction in transmit driver power; 3) up to 6× improvement in transmit jitter tolerance; and 4) a 25- to 40-mV improvement in comparator offset tolerance with 3 × smaller swing.
| Original language | English (US) |
|---|---|
| Article number | 5464335 |
| Pages (from-to) | 359-363 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 57 |
| Issue number | 5 |
| DOIs | |
| State | Published - May 2010 |
Keywords
- Analog-to-digital converter
- Backplane transceivers
- Clock jitter
- Comparative offset
- Energy-efficiency
- Forward error correction
- High-speed links
- Transmit driver
ASJC Scopus subject areas
- Electrical and Electronic Engineering