Design of crystal-oscillator frequency quadrupler for low-jitter clock multipliers

Implementation of low-noise power-efficient clock multipliers requires low-noise high-frequency reference clocks. This paper presents ways to generate such reference clocks at four times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216-MHz reference clock with an integrated jitter of 77 fs_rms is generated from a 54-MHz Pierce XO. A ring oscillator-based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65-nm CMOS process, the proposed clock multiplier occupies an active area of 0.16 mm² and achieves 366 fs_rms integrated jitter at 4.752-GHz output frequency while consuming 6.5-mW power from a 1.0-V supply of which 1.5 mW is consumed in the quadrupler.