Design of crystal-oscillator frequency quadrupler for low-jitter clock multipliers

Karim M. Megawer, Ahmed Elkholy, Mostafa Gamal Ahmed, Ahmed Elmallah, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

Implementation of low-noise power-efficient clock multipliers requires low-noise high-frequency reference clocks. This paper presents ways to generate such reference clocks at four times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216-MHz reference clock with an integrated jitter of 77 fsrms is generated from a 54-MHz Pierce XO. A ring oscillator-based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65-nm CMOS process, the proposed clock multiplier occupies an active area of 0.16 mm2 and achieves 366 fsrms integrated jitter at 4.752-GHz output frequency while consuming 6.5-mW power from a 1.0-V supply of which 1.5 mW is consumed in the quadrupler.

Original languageEnglish (US)
Article number8486730
Pages (from-to)65-74
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number1
DOIs
StatePublished - Jan 2019

Keywords

  • Crystal oscillator (XO)
  • digitally controlled oscillator (DCO)
  • duty-cycle correction
  • frequency quadrupler
  • injection-locked clock multiplier (ILCM)
  • jitter
  • least mean square (LMS)
  • ring oscillator (RO)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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