TY - JOUR
T1 - Design of crystal-oscillator frequency quadrupler for low-jitter clock multipliers
AU - Megawer, Karim M.
AU - Elkholy, Ahmed
AU - Gamal Ahmed, Mostafa
AU - Elmallah, Ahmed
AU - Kumar Hanumolu, Pavan
N1 - Manuscript received April 22, 2018; revised July 25, 2018 and September 15, 2018; accepted September 23, 2018. Date of publication October 9, 2018; date of current version January 14, 2019. This paper was approved by Guest Editor Yohan Frans. This work was supported in part by Analog Devices. (Corresponding author: Karim M. Megawer.) The authors are with the Department of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Urbana, IL 61801 USA (e-mail: [email protected]).
PY - 2019/1
Y1 - 2019/1
N2 - Implementation of low-noise power-efficient clock multipliers requires low-noise high-frequency reference clocks. This paper presents ways to generate such reference clocks at four times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216-MHz reference clock with an integrated jitter of 77 fsrms is generated from a 54-MHz Pierce XO. A ring oscillator-based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65-nm CMOS process, the proposed clock multiplier occupies an active area of 0.16 mm2 and achieves 366 fsrms integrated jitter at 4.752-GHz output frequency while consuming 6.5-mW power from a 1.0-V supply of which 1.5 mW is consumed in the quadrupler.
AB - Implementation of low-noise power-efficient clock multipliers requires low-noise high-frequency reference clocks. This paper presents ways to generate such reference clocks at four times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216-MHz reference clock with an integrated jitter of 77 fsrms is generated from a 54-MHz Pierce XO. A ring oscillator-based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65-nm CMOS process, the proposed clock multiplier occupies an active area of 0.16 mm2 and achieves 366 fsrms integrated jitter at 4.752-GHz output frequency while consuming 6.5-mW power from a 1.0-V supply of which 1.5 mW is consumed in the quadrupler.
KW - Crystal oscillator (XO)
KW - digitally controlled oscillator (DCO)
KW - duty-cycle correction
KW - frequency quadrupler
KW - injection-locked clock multiplier (ILCM)
KW - jitter
KW - least mean square (LMS)
KW - ring oscillator (RO)
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U2 - 10.1109/JSSC.2018.2872539
DO - 10.1109/JSSC.2018.2872539
M3 - Article
AN - SCOPUS:85054641595
SN - 0018-9200
VL - 54
SP - 65
EP - 74
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 1
M1 - 8486730
ER -