Abstract
With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. Therefore, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant margins in the design of an ARM microprocessor. A prototype stochastic ARM1136 processor was implemented in TSMC 90nm technology. Two circuit-level techniques, Razor and Surger, are exploited to form a hybrid error detection mechanism by observing both global and local timing information. To enable the deployment of aggressive voltage scaling with hardware-based error tolerance mechanism, we propose an activity-driven optimization flow to reshape the slack distribution based on path-activation probability. The chip achieves a frequency of 250MHz at worst case with 48.82mW power consumption. The overall power overhead of the proposed error tolerance mechanism is about 25% (hold-fixing latches 15.25% plus Razor 10.53%). The energy saving through design margins elimination is 51% (an average of the three corner cases) and a 42.8% saving was measured at the lowest operation voltage.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016 |
| Publisher | IEEE Computer Society |
| Pages | 217-222 |
| Number of pages | 6 |
| ISBN (Electronic) | 9781509013661 |
| DOIs | |
| State | Published - Apr 19 2017 |
| Event | 29th IEEE International System on Chip Conference, SOCC 2016 - Seattle, United States Duration: Sep 6 2016 → Sep 9 2016 |
Other
| Other | 29th IEEE International System on Chip Conference, SOCC 2016 |
|---|---|
| Country | United States |
| City | Seattle |
| Period | 9/6/16 → 9/9/16 |
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Keywords
- Error Correction
- Error Detection
- Error Resilience
- Razor
- Stochastic Processor
- Surger
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering
- Electrical and Electronic Engineering
Cite this
Design of a power-efficient ARM processor with a timing-error detection and correction mechanism. / Chen, Sao Jie; Liu, Grace; Yang, Hsin Ping; Luo, Cheng Hao; Hwu, Wen-Mei W.
Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016. IEEE Computer Society, 2017. p. 217-222 7905471.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Design of a power-efficient ARM processor with a timing-error detection and correction mechanism
AU - Chen, Sao Jie
AU - Liu, Grace
AU - Yang, Hsin Ping
AU - Luo, Cheng Hao
AU - Hwu, Wen-Mei W
PY - 2017/4/19
Y1 - 2017/4/19
N2 - With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. Therefore, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant margins in the design of an ARM microprocessor. A prototype stochastic ARM1136 processor was implemented in TSMC 90nm technology. Two circuit-level techniques, Razor and Surger, are exploited to form a hybrid error detection mechanism by observing both global and local timing information. To enable the deployment of aggressive voltage scaling with hardware-based error tolerance mechanism, we propose an activity-driven optimization flow to reshape the slack distribution based on path-activation probability. The chip achieves a frequency of 250MHz at worst case with 48.82mW power consumption. The overall power overhead of the proposed error tolerance mechanism is about 25% (hold-fixing latches 15.25% plus Razor 10.53%). The energy saving through design margins elimination is 51% (an average of the three corner cases) and a 42.8% saving was measured at the lowest operation voltage.
AB - With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. Therefore, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant margins in the design of an ARM microprocessor. A prototype stochastic ARM1136 processor was implemented in TSMC 90nm technology. Two circuit-level techniques, Razor and Surger, are exploited to form a hybrid error detection mechanism by observing both global and local timing information. To enable the deployment of aggressive voltage scaling with hardware-based error tolerance mechanism, we propose an activity-driven optimization flow to reshape the slack distribution based on path-activation probability. The chip achieves a frequency of 250MHz at worst case with 48.82mW power consumption. The overall power overhead of the proposed error tolerance mechanism is about 25% (hold-fixing latches 15.25% plus Razor 10.53%). The energy saving through design margins elimination is 51% (an average of the three corner cases) and a 42.8% saving was measured at the lowest operation voltage.
KW - Error Correction
KW - Error Detection
KW - Error Resilience
KW - Razor
KW - Stochastic Processor
KW - Surger
UR - http://www.scopus.com/inward/record.url?scp=85019124502&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85019124502&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2016.7905471
DO - 10.1109/SOCC.2016.7905471
M3 - Conference contribution
SP - 217
EP - 222
BT - Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016
PB - IEEE Computer Society
ER -