Design of a power-efficient ARM processor with a timing-error detection and correction mechanism

Sao Jie Chen, Grace Liu, Hsin Ping Yang, Cheng Hao Luo, Wen-Mei W Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. Therefore, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant margins in the design of an ARM microprocessor. A prototype stochastic ARM1136 processor was implemented in TSMC 90nm technology. Two circuit-level techniques, Razor and Surger, are exploited to form a hybrid error detection mechanism by observing both global and local timing information. To enable the deployment of aggressive voltage scaling with hardware-based error tolerance mechanism, we propose an activity-driven optimization flow to reshape the slack distribution based on path-activation probability. The chip achieves a frequency of 250MHz at worst case with 48.82mW power consumption. The overall power overhead of the proposed error tolerance mechanism is about 25% (hold-fixing latches 15.25% plus Razor 10.53%). The energy saving through design margins elimination is 51% (an average of the three corner cases) and a 42.8% saving was measured at the lowest operation voltage.

Original languageEnglish (US)
Title of host publicationProceedings - 29th IEEE International System on Chip Conference, SOCC 2016
EditorsKaran Bhatia, Massimo Alioto, Danella Zhao, Andrew Marshall, Ramalingam Sridhar
PublisherIEEE Computer Society
Pages217-222
Number of pages6
ISBN (Electronic)9781509013661
DOIs
StatePublished - Jul 2 2016
Event29th IEEE International System on Chip Conference, SOCC 2016 - Seattle, United States
Duration: Sep 6 2016Sep 9 2016

Publication series

NameInternational System on Chip Conference
Volume0
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Other

Other29th IEEE International System on Chip Conference, SOCC 2016
CountryUnited States
CitySeattle
Period9/6/169/9/16

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Keywords

  • Error Correction
  • Error Detection
  • Error Resilience
  • Razor
  • Stochastic Processor
  • Surger

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Chen, S. J., Liu, G., Yang, H. P., Luo, C. H., & Hwu, W-M. W. (2016). Design of a power-efficient ARM processor with a timing-error detection and correction mechanism. In K. Bhatia, M. Alioto, D. Zhao, A. Marshall, & R. Sridhar (Eds.), Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016 (pp. 217-222). [7905471] (International System on Chip Conference; Vol. 0). IEEE Computer Society. https://doi.org/10.1109/SOCC.2016.7905471