Design methodology for high-speed iterative decoder architectures

Keyphrases

• Design Methodology 100%
• Posteriori Probability 100%
• Soft Output 100%
• Iterative Decoder 100%
• Low Power 50%
• Window Size 50%
• Speed-power 50%
• Step Processes 50%
• Time Scheduling 50%
• Forward-backward 50%
• Storage Overhead 50%
• Conventional Architecture 50%
• State-dependent Delay 50%
• Decoding Algorithm 50%
• Graphical Approach 50%
• VLSI Architecture 50%
• Turbo Decoder 50%
• Recursion Pattern 50%
• Decoding Delay 50%
• Minimal Delay 50%
• Output Metrics 50%
• Recursion Equations 50%

Engineering

• Posteriori Probability 100%
• Soft Output 100%
• Metrics 50%
• Step Process 50%
• Input State 50%
• Decoding Algorithm 50%

Computer Science

• Posteriori Probability 100%
• Storage Overhead 50%
• Conventional Architecture 50%
• Decoding Algorithm 50%
• Very large-scale integration (VLSI) architecture 50%
• Recursion Equation 50%