Design Guidelines and Limitations of Multilayer Two-dimensional Vertical Tunneling FETs for UltraLow Power Logic Applications

Shang Chun Lu, Yuanchen Chu, Youngseok Kim, Mohamed Y. Mohamed, Gerhard Klimeck, Tomas Palacios, Umberto Ravaioli

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

New designs for vertical 2D-materials-based TFETs are proposed in this paper adopting asymmetric layer numbers for the top and bottom layer with undoped source/drain using Black Phosphorus as an example. The results show that abrupt turn-on and I on /I off > 10 5 can be sustained when the channel length is down to sub-5 nm. The results are benchmarked against other TFETs based on promising 2D materials homo-/hetero-structures, meanwhile, the limitations, as well as guidelines, are presented.

Original languageEnglish (US)
Title of host publicationSISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages138-140
Number of pages3
ISBN (Electronic)9781538667880
DOIs
StatePublished - Nov 28 2018
Event2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018 - Austin, United States
Duration: Sep 24 2018Sep 26 2018

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume2018-September

Other

Other2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018
CountryUnited States
CityAustin
Period9/24/189/26/18

Keywords

  • DFT
  • Non-equilibrium Green's Function
  • TMDCs
  • Two-dimensional Materials Heterojunctions
  • black phosphorus
  • tunnel FETs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modeling and Simulation

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