Design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA

Keyphrases

• Neural Network 100%
• Design Flow 100%
• Bit-width 100%
• Embedded FPGA 100%
• Low-bit 100%
• Neural Network Accelerator 66%
• High Performance 33%
• Computational Efficiency 33%
• Network Accuracy 33%
• FPGA Implementation 33%
• Low Power Consumption 33%
• FPGA-based 33%
• Low Latency 33%
• Resource Constraints 33%
• Power Constraint 33%
• Network Computation 33%
• Edge Devices 33%
• Large-scale Neural Networks 33%
• Design Space Exploration 33%
• Energy Solutions 33%
• Network Training 33%
• Network Deployment 33%
• Quantization Scheme 33%
• Training Base 33%
• Edge Computing 33%
• Flow Cover 33%
• Hybrid Quantization 33%

Computer Science

• Neural Network 100%
• Field Programmable Gate Arrays 100%
• Lower Energy Consumption 20%
• Power Constraint 20%
• Resource Constraint 20%
• Energy Efficient 20%
• Design-Space Exploration 20%
• Hardware Designer 20%
• Edge Computing 20%
• Graphics Processing Unit 20%

Engineering

• Field Programmable Gate Arrays 100%
• Design Flow 100%
• Graphics Processing Unit 20%
• Simplifies 20%
• Design Space 20%
• Power Constraint 20%
• Network Training 20%
• Edge Computing 20%