Design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA

Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Neural network accelerators with low latency and low energy consumption are desirable for edge computing. To create such accelerators, we propose a design flow for accelerating the extremely low bit-width neural network (ELB-NN) in embedded FPGAs with hybrid quantization schemes. This flow covers both network training and FPGA-based network deployment, which facilitates the design space exploration and simplifies the tradeoff between network accuracy and computation efficiency. Using this flow helps hardware designers to deliver a network accelerator in edge devices under strict resource and power constraints. We present the proposed flow by supporting hybrid ELB settings within a neural network. Results show that our design can deliver very high performance peaking at 10.3 TOPS and classify up to 325.3 image/s/watt while running large-scale neural networks for less than 5W using embedded FPGA. To the best of our knowledge, it is the most energy efficient solution in comparison to GPU or other FPGA implementations reported so far in the literature.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages163-169
Number of pages7
ISBN (Electronic)9781538685174
DOIs
StatePublished - Nov 9 2018
Event28th International Conference on Field-Programmable Logic and Applications, FPL 2018 - Dublin, Ireland
Duration: Aug 26 2018Aug 30 2018

Publication series

NameProceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018

Other

Other28th International Conference on Field-Programmable Logic and Applications, FPL 2018
CountryIreland
CityDublin
Period8/26/188/30/18

Keywords

  • DNN
  • ELB NN
  • FPGA
  • hybrid quantization

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture
  • Software

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  • Cite this

    Wang, J., Lou, Q., Zhang, X., Zhu, C., Lin, Y., & Chen, D. (2018). Design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA. In Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018 (pp. 163-169). [8533487] (Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2018.00035