DESIGN CHOICES FOR THE HPSm MICROPROCESSOR CHIP.

Wen mei Hwu; Yale N. Patt

DESIGN CHOICES FOR THE HPSm MICROPROCESSOR CHIP.

Research output: Contribution to journal › Conference article

Abstract

HPS (High Performance Substrate) is a parallel microarchitecture design style where data flow techniques are used to coordinate out-of-order execution. This paper discusses the design choices we have regarding several important issues in the HPSm design. These issues are horizontal concurrency, active window size, checkpoints for handling conditional branches and exceptions, forwarding delay, operand scheduling, memory data dependency handling, and value buffering.

Original language	English (US)
Pages (from-to)	330-336
Number of pages	7
Journal	Proceedings of the Hawaii International Conference on System Science
Volume	1
State	Published - Jan 1 1987
Externally published	Yes

ASJC Scopus subject areas

Computer Science(all)

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Hwu, W. M., & Patt, Y. N. (1987). DESIGN CHOICES FOR THE HPSm MICROPROCESSOR CHIP. Proceedings of the Hawaii International Conference on System Science, 1, 330-336.

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abstract = "HPS (High Performance Substrate) is a parallel microarchitecture design style where data flow techniques are used to coordinate out-of-order execution. This paper discusses the design choices we have regarding several important issues in the HPSm design. These issues are horizontal concurrency, active window size, checkpoints for handling conditional branches and exceptions, forwarding delay, operand scheduling, memory data dependency handling, and value buffering.",

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N2 - HPS (High Performance Substrate) is a parallel microarchitecture design style where data flow techniques are used to coordinate out-of-order execution. This paper discusses the design choices we have regarding several important issues in the HPSm design. These issues are horizontal concurrency, active window size, checkpoints for handling conditional branches and exceptions, forwarding delay, operand scheduling, memory data dependency handling, and value buffering.

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