Design and optimization of vertical SiGe thyristors for on-chip BSD protection

Sopan Joshi, Richard Ida, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

In this paper, we present extensive measurement results investigating the design and optimization of vertical SiGe thyristors for use as ESD protection elements in RF integrated circuits. Experiments include variations of the anode material, contact geometry, and buried layer, as well as a detailed study of optimal area scaling. RF characterization using s-parameter data is presented.

Original languageEnglish (US)
Pages (from-to)586-593
Number of pages8
JournalIEEE Transactions on Device and Materials Reliability
Volume4
Issue number4
DOIs
StatePublished - Dec 1 2004

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Thyristors
Integrated circuits
Anodes
Geometry
Experiments

Keywords

  • Electrostatic discharges
  • Heterojunction bipolar transistors
  • Reliability
  • Thyristors

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

Design and optimization of vertical SiGe thyristors for on-chip BSD protection. / Joshi, Sopan; Ida, Richard; Rosenbaum, Elyse.

In: IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 4, 01.12.2004, p. 586-593.

Research output: Contribution to journalArticle

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