Design and analysis of reconfigurable embedded GNSS receivers using model-based design tools

Over the next decade, civilian users will have access to multiple GNSS signal frequencies and constellations. This drastic increase in signals and their frequencies creates substantial opportunities and requirements for analysis and validation. Such analysis and validation is of significant importance from an aviation integrity perspective. The ultimate goal of our research efforts is to develop a standalone reconfigurable platform capable of tracking and monitoring multiple constellations and frequencies as and when they commence transmission. This platform will also be utilized to test and verify new receiver processing algorithms currently under development. It must be capable of running in real-time to ensure signals can be monitored on a 24x7 basis. As a first step in this direction, we designed and validated a standalone L1 C/A receiver which runs in real-time on a Xilinx University Program Virtex-II Pro Development Board. This board features a Virtex-II Pro FPGA with two on-chip PowerPC 405 32-bit RISC hardcore processors. This feature of the FPGA fabric facilitates the development of reconfigurable embedded GNSS receivers which do not require the resources of a Host PC or a dedicated DSP processor. The entire system was designed using the Xilinx System Generator for DSP, a modeling and implementation tool for high-performance DSP systems. Such a model-based design approach facilitates rapid system development and prototyping thereby enabling system modifications and upgrades to be implemented in a short time span.