Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the proposed FTL continuously tunes the oscillator's free-running frequency to ensure robust operation across PVT variations. The FTL resolves the race condition existing in injection-locked PLLs by decoupling frequency tuning from the injection path, such that the phase-locking condition is only determined by the injection path. This paper also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection-locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25\;\text{mm}^2. The prototype ILCM generates output clock in the range of 6.75-8.25 GHz by multiplying the reference clock by 64. It achieves superior integrated jitter performance of 190\;\text{fs}-{\text{rms}}, while consuming 2.25 mW power. This translates to an excellent figure-of-merit (FoM) of -251\;\text{dB}, which is the best reported high-frequency clock multiplier.

Original languageEnglish (US)
Article number7297803
Pages (from-to)3160-3174
Number of pages15
JournalIEEE Journal of Solid-State Circuits
Volume50
Issue number12
DOIs
StatePublished - Dec 2015

Keywords

  • Clock multiplier
  • DCO
  • PLLs
  • digital phase-locked loop (PLL)
  • frequency multiplier
  • frequency tracking
  • impulse sensitivity function (ISF)
  • injection locking
  • multiplying injection-locked oscillator (MILO)
  • phase domain response (PDR)
  • phase noise
  • pulse
  • reference spur
  • rms jitter
  • sub-harmonic locking
  • sub-sampling (SS)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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