DeNovoND: Efficient hardware for disciplined nondeterminism

Hyojin Sung, Rakesh Komuravelli, Sarita V. Adve

Research output: Contribution to journalArticlepeer-review


Recent research in disciplined shared-memory programming models presents a unique opportunity for rethinking the multicore memory hierarchy for better efficiency in terms of complexity, performance, and energy. The DeNovo hardware system showed that for deterministic programs written using such disciplined models, hardware can be much more efficient than the current state of the art. For DeNovo to be adopted by commercial systems, however, it is necessary to extend it to support nondeterministic applications as well; for example, applications using lock synchronization. This article proposes DeNovoND, a system that provides support for disciplined nondeterministic codes with locks while retaining the simplicity, performance, and energy benefits of DeNovo. The authors designed and implemented simple memory consistency semantics for safe nondeterminism using distributed queue-based locks and access signatures. The resulting protocol avoids transient states, invalidation traffic, directory sharer-lists, and false sharing, which are all significant sources of inefficiency in existing protocols. Their experiments showed that DeNovoND provides comparable or better execution time for applications designed for lock synchronization. In addition, it incurs 33 percent less network traffic on average relative to a state-of-the-art invalidation-based protocol, which directly translates into energy savings.

Original languageEnglish (US)
Article number6756708
Pages (from-to)138-148
Number of pages11
JournalIEEE Micro
Issue number3
StatePublished - 2014


  • cache coherence
  • disciplined programming models
  • energy efficiency
  • hardware
  • memory hierarchy
  • memory models
  • multicore
  • shared-memory architecture

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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