DeNovo: Rethinking the memory hierarchy for disciplined parallelism

Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V Adve, Vikram Sadanand Adve, Nicholas P. Carter, Ching Tsun Chou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

For parallelism to become tractable for mass programmers, shared-memory languages and environments must evolve to enforce disciplined practices that ban "wild shared-memory behaviors;" e.g., unstructured parallelism, arbitrary data races, and ubiquitous non-determinism. This software evolution is a rare opportunity for hardware designers to rethink hardware from the ground up to exploit opportunities exposed by such disciplined software models. Such a co-designed effort is more likely to achieve many-core scalability than a software-oblivious hardware evolution. This paper presents De-Novo, a hardware architecture motivated by these observations. We show how a disciplined parallel programming model greatly simplifies cache coherence and consistency, while enabling a more efficient communication and cache architecture. The DeNovo coherence protocol is simple because it eliminates transient states - verification using model checking shows 15X fewer reachable states than a state-of-theart implementation of the conventional MESI protocol. The De- Novo protocol is also more extensible. Adding two sophisticated optimizations, flexible communication granularity and direct cache-to-cache transfers, did not introduce additional protocol states (unlike MESI). Finally, DeNovo shows better cache hit rates and network traffic, translating to better performance and energy. Overall, a disciplined shared-memory programming model allows DeNovo to seamlessly integrate message passing-like interactions within a global address space for improved design complexity, performance, and efficiency.

Original languageEnglish (US)
Title of host publicationProceedings - 2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011
Pages155-166
Number of pages12
DOIs
StatePublished - Dec 1 2011
Event20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011 - Galveston, TX, United States
Duration: Oct 10 2011Oct 14 2011

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Other

Other20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011
Country/TerritoryUnited States
CityGalveston, TX
Period10/10/1110/14/11

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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