Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective

Houxiang Ji, Srikar Vanavasam, Yang Zhou, Qirong Xia, Jinghan Huang, Yifan Yuan, Ren Wang, Pekon Gupta, Bhushan Chitlur, Ipoom Jeong, Nam Sung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

CXL is the latest interconnect technology built on PCIe, providing three protocols to facilitate three distinct types of devices, each with unique capabilities. Among these devices, a CXL Type-2 device has become commercially available, followed by CXL Type-3 devices. Therefore, it is timely to understand capabilities and characteristics of the CXL Type-2 device, as well as explore suitable applications. In this work, first, we delve into three key features of a CXL Type-2 device: cache-coherent device accelerator to host memory, device accelerator to device memory, and host CPU to device memory accesses. Second, using microbenchmarks, we comprehensively characterize the latency and bandwidth of these memory accesses with a CXL Type-2 device, and then compare them with those of equivalent memory accesses with comparable devices, such as emulated CXL Type-2, CXL Type-3, and PCIe devices. Lastly, as applications that exploit the unique capabilities of a CXL Type-2 device, we propose two CXL-based Linux memory optimization features: compressed RAM cache for swap (zswap) and memory deduplication (ksm). Our evaluation shows that Redis, when running with traditional CPU-based zswap and ksm, suffers from a tail latency increase of 4.5-10.3× compared to Redis running alone. While PCIe-based zswap and ksm still experience a tail latency increase of up to 8.1×, CXL-based zswap and ksm practically eliminate the tail latency increase with faster and more efficient host-device communication than PCIe-based zswap and ksm.

Original languageEnglish (US)
Title of host publicationProceedings - 2024 57th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2024
PublisherIEEE Computer Society
Pages1504-1517
Number of pages14
ISBN (Electronic)9798350350579
DOIs
StatePublished - 2024
Event57th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2024 - Austin, United States
Duration: Nov 2 2024Nov 6 2024

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Conference

Conference57th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2024
Country/TerritoryUnited States
CityAustin
Period11/2/2411/6/24

Keywords

  • compute express link
  • heterogeneous computing

ASJC Scopus subject areas

  • Hardware and Architecture

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