The demonstration of an optoelectronic sorter unit is presented. This sorter is constructed using a recirculating architecture that passes data optically between two smart-pixel arrays. Each array is implemented using a hybrid combination of CMOS logic and vertical cavity surface emitting lasers (VCSELs). Since implementation of this system is intended as a tool for evaluating the technological issues associated with CMOS/VCSEL smart-pixel device, the system implementation is designed to minimize interconnect complexity while focusing on the smart-pixel design and analysis. A power budget analysis indicates that the photoreceivers require a minimum of 130 μW of optical input power, which leads to a VCSEL power requirement of ∼415 μW. The frequency response of the photoreceivers and logic circuit reveals that the photodetector limits the operaton to ∼3 MHz, which is an order of magnitude slower than the logic circuits frequency limit.
- CMOS/VCSEL hybrid devices
- Digital optical computing
- Optoelectronic smart pixels
ASJC Scopus subject areas
- Atomic and Molecular Physics, and Optics