Delay optimal low-power circuit clustering for FPGAs with dual supply voltages

Deming Chen, Jason Cong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high supply voltage (high-Vdd) or a low supply voltage (low-Vdd). We carry out the clustering procedure with the guarantee that the delay of the circuit under the general delay model is optimal, and in the meantime, logic blocks on the non-critical paths can be driven by low-Vdd to save power. We explore a set of dual-Vdd combinations to find the best ratio between low-Vdd and high-Vdd to achieve the largest power reduction. Experimental results show that our clustering algorithm can achieve power savings by 20.3% on average compared to the clustering result for an FPGA with a single high-Vdd. To our knowledge, this is the first work on dual-Vdd clustering for FPGA architectures.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
PublisherAssociation for Computing Machinery
Pages70-73
Number of pages4
ISBN (Print)1581139292, 9781581139297
DOIs
StatePublished - 2004
Externally publishedYes
EventProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 - Newport Beach, CA, United States
Duration: Aug 9 2004Aug 11 2004

Publication series

NameProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Other

OtherProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
Country/TerritoryUnited States
CityNewport Beach, CA
Period8/9/048/11/04

Keywords

  • Circuit clustering
  • Dual supply voltage
  • Low-power FPGA

ASJC Scopus subject areas

  • Engineering(all)

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