Abstract
The trench architecture and process flow for a 170 V complementary bipolar technology with trench isolation and bonded wafer substrates is described. Electrical and material (micro-Raman) characterization is used to show that the process architecture and optimized process flow results in defect free silicon device regions.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE International SOI Conference |
| Editors | Anon |
| Publisher | IEEE |
| Pages | 151-152 |
| Number of pages | 2 |
| State | Published - 1998 |
| Externally published | Yes |
| Event | Proceedings of the 1998 IEEE International SOI Conference - Stuart, FL, USA Duration: Oct 5 1998 → Oct 8 1998 |
Other
| Other | Proceedings of the 1998 IEEE International SOI Conference |
|---|---|
| City | Stuart, FL, USA |
| Period | 10/5/98 → 10/8/98 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering