Defect free deep trench isolation for high voltage bipolar application on SOI wafer

W. Yindeepol, Rashid Bashir, J. M. McGregor, K. C. Brown, I. De Wolf, J. De Santis, A. Ahmed

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The trench architecture and process flow for a 170 V complementary bipolar technology with trench isolation and bonded wafer substrates is described. Electrical and material (micro-Raman) characterization is used to show that the process architecture and optimized process flow results in defect free silicon device regions.

Original languageEnglish (US)
Title of host publicationIEEE International SOI Conference
Editors Anon
PublisherIEEE
Pages151-152
Number of pages2
StatePublished - Dec 1 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International SOI Conference - Stuart, FL, USA
Duration: Oct 5 1998Oct 8 1998

Other

OtherProceedings of the 1998 IEEE International SOI Conference
CityStuart, FL, USA
Period10/5/9810/8/98

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Yindeepol, W., Bashir, R., McGregor, J. M., Brown, K. C., De Wolf, I., De Santis, J., & Ahmed, A. (1998). Defect free deep trench isolation for high voltage bipolar application on SOI wafer. In Anon (Ed.), IEEE International SOI Conference (pp. 151-152). IEEE.